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      Ports		      []
      Position		      [35, 57, 144, 108]
      BackgroundColor	      "lightBlue"
      Priority		      "1"
      List {
	ListType		RTWdata
	NumBusyPort		"-1"
      }
      SourceBlock	      "dsPICdrivers/Master"
      SourceType	      "Master"
      TimeStepType	      "Timer1"
      picType		      "33fJ256MC710"
      fcy		      "20000000"
      Quartz_33f	      "40e6"
      PLLActive_33f	      off
      fcyDesired_33f	      "0"
      tmr1		      "[1  19999  0]"
      tmr1Info		      "Time Step : 0.001  ;   Error : 0%  PR1=19999"
      tmr2345		      "[0  0  0  0  0  0  0  0]"
      tmr2345cfg	      "[-1 -1 -1 -1 -1 -1 -1 -1]"
      IOautoConf	      on
      typePort		      "[ 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  4  5  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 ]"
      TRIS		      "[ 65535  65535  65535  65535  65535  65535  65535 ]"
      ADPCFG		      "0"
      MasterBusyPort	      "None"
      MasterOverloadPort      "None"
      FOSC		      "Quartz (XT - HS)"
      TempProtection_33f      "TEMP_ON"
      FPBOR		      "<empty>"
      PWRT		      "disable"
      MCLR		      "<empty>"
      PowerSave		      off
    }
    Block {
      BlockType		      Sin
      Name		      "Sine Wave"
      Ports		      [0, 1]
      Position		      [115, 230, 145, 260]
      SineType		      "Sample based"
      Amplitude		      "2^12/2"
      Bias		      "2^12/2"
      Samples		      "20"
      SampleTime	      "0.01"
      VectorParams1D	      off
    }
    Block {
      BlockType		      Reference
      Name		      "TX Output Multiplexed\nfor Matlab / Labview"
      Tag		      "dsPIC_TX_Multiplexed"
      Ports		      [1]
      Position		      [635, 220, 780, 250]
      Priority		      "5"
      SourceBlock	      "dsPICdrivers/Serial PORT/TX Output Multiplexed\nfor Matlab // Labview"
      SourceType	      "send structured data frame to Matlab / Labview"
      UART		      "2"
      CleverSpreadingChk      on
      CleverSpreading	      "1"
      CHANNEL		      "[0]"
      CHANNELBLOCKED	      "[]"
      CHANNELBLOCKED_BITEWISE "0"
      Status		      "OK"
    }
    Block {
      BlockType		      Reference
      Name		      "UART Configuration"
      Tag		      "dsPIC_config_UART"
      Ports		      []
      Position		      [385, 29, 486, 59]
      BackgroundColor	      "lightBlue"
      Priority		      "2"
      List {
	ListType		RTWdata
	RxBufferSize		"32"
      }
      SourceBlock	      "dsPICdrivers/Serial PORT/UART Configuration"
      SourceType	      "Configure UART"
      UART		      "2"
      proposed_BAUD	      "9600"
      ALT_TX_RX		      on
      InterruptTxWhen	      "When Transmit Buffer is empty"
      TXInterruptPri	      "1"
      TxBufferSize	      "32"
      TXEN		      on
      InterruptRxWhen	      "When Receive Buffer is full (contain 4 characters)"
      RXInterruptPri	      "2"
      RxBufferSize	      "32"
      BAUD		      "9600"
      UxBRG		      "129"
      Info		      "UxBRG = 129   ||  Real Baud : 9615   ||  % error : 0.16026  ||  max 0.96154 Bytes / Step"
      RealBaud		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "dbl-click to open\nGraphical interface"
      Ports		      []
      Position		      [565, 28, 665, 78]
      BackgroundColor	      "cyan"
      DropShadow	      on
      SourceBlock	      "dsPICdrivers/Serial PORT/dbl-click to open\nGraphical interface"
      SourceType	      ""
      ShowPortLabels	      "FromPortIcon"
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      Nothing		      "0"
    }
    Line {
      SrcBlock		      "Sine Wave"
      SrcPort		      1
      DstBlock		      "Data Type Conversion"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Data Type Conversion"
      SrcPort		      1
      Points		      [10, 0; 0, -5; 145, 0; 0, -5]
      DstBlock		      "TX Output Multiplexed\nfor Matlab / Labview"
      DstPort		      1
    }
  }
}
# Finite State Machines
#
#    Stateflow Version 6.7 (R2007b) dated Aug  7 2007, 16:48:14
#
#


Stateflow {
  machine {
    id			    1
    name		    "Source_one_sinus_to_RS_9600_on_MC"
    created		    "09-Jul-2008 17:05:56"
    isLibrary		    0
    firstTarget		    2
    sfVersion		    67014000.000001
  }
  target {
    id			    2
    name		    "sfun"
    description		    "Default Simulink S-Function Target."
    machine		    1
    linkNode		    [1 0 3]
  }
  target {
    id			    3
    name		    "rtw"
    codeFlags		    " comments=1 statebitsets=1 databitsets=1 emitlogicalops=1 elseifdetection=1 constantfolding=1 redundantloadelimination=0 preservenames=0 preservenameswithparent=0 exportcharts=0"
    machine		    1
    linkNode		    [1 2 0]
  }
}