Hi Lubin,



I am making a sampling using the OC(HW) and ADC.

In the dialog of OC(HW), we can set the period for the PWM output.

However, I am not clear about setting the duty cycle.

Could you explain exactly what the set and reset mean in the block?

Thanks in advance.



Quan

Could you please have a look on the block's page : http://www.kerhuel.eu/wiki/Block/Output_Compare_HW



Unfortunatly, I will not have time to draw something (that would make it clearer)



If there are unclear point, please let me know.



Lubin

Hi Lubin,



Sorry for bothering you again.

I have read the block page many times, still I cannot get what I want.

Attached is a graph got from the example of Hyper Sampling.

Could you explain how the duty cycle is decided and why there is a "+" between the set and reset inputs?

Thanks very much.



Quan

Hi Quan,



I respond quicky, sorry if there are imprecision.



OC works with a counter. For a given periode (set within the block) the counter will count from 0 to a number, let say it is 1000 here, this number is given in OCmax (it depends on your quartz).



- The ADC starts conversion when the counter is reset, ie, goes from 1000 to 0.

- The OC output is set to 1 when the counter reach the Tset value.

- The OC output is set to 0 when the counter reach the Treset value.



For example,

- if Tset value 250 and Treset value is 350, you will get a PWM duty cycle of 10% on the OC output. ADC will starts conversion while the OC output is 0

- if Tset value 950 and Treset value is 50, you will also get a PWM duty cycle of 10% on the OC output. ADC will starts conversion while the OC output is 1



Please feel free to add any usefull explanation on the Wiki page about OC(HW)

http://www.kerhuel.eu/wiki/Block/Output_Compare_HW

Hi Lubin,



Thanks for your patient explanation.

I will add some detailed explanation for OC(HW).



Quan